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semiconductor group 1 1998-10-01 overview the hyb 39s163200tq are dual bank synchronous graphics drams (sgram) organized as 2 banks 256 kbit 32 with built-in graphics features. these synchronous devices achieve high speed data transfer rates up to 143 mhz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with an advanced 64mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous graphics dram products, both electrically and mechanically. ras , cas , we , dsf and cs are pulsed signals which are examined at the positive edge of each externally applied clock. internal chip operating modes are defined by combinations of these signals. a ten bit address bus accepts address data in the conventional ras/cas multiplexing style. ten row address bits (a0 - a9) and a bank select ba are strobed with ras . column address bits plus a bank select are strobed with cas . prior to any access operation, the cas latency, burst length and burst sequence must be programmed into the device by address inputs during a mode register set cycle. an auto precharge function may be enabled to provide a self-timed row precharge. this is initiated at the end of the burst sequence. in addition, it features the write per bit, the block write and the masked block write ? high performance: ? single pulsed ras interface ? programmable cas latency: 2, 3 ? fully synchronous to positive clock edge ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 and full page for sequential 1, 2, 4, 8 for interleave -6 -7 -7 -8 units f ck 166 125 125 125 mhz latency 3233 - t ck3 6878ns t ac3 5.5 5.5 5.5 6 ns ? special mode registers ? two color registers ? burst read with single write operation ? block write and write-per-bit capability ? byte controlled by dqm0-3 ? auto precharge and auto refresh modes ? suspend mode and power down mode ? 2k refresh cycles/32 ms ? t ac = 5 ns ? t setup / t hold = 2 ns/1 ns ? latency 2 @ 125 mhz ? random column address every clk (1-n rule) ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs hyb 39s13620tq-6/-7/-8
hyb 39s16320tq-6/-7/-8 semiconductor group 2 1998-10-01 functions. by having a programmable mode register and special mode register, the system can select the best suitable modes to maximize its performance. operating the two memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 143 mhz is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3 v 0.3 v power supply and are available in 100 pin tqfp package. features ? all signals fully synchronous to the positiv edge of the system clock ? programmable burst lengths: 1, 2, 4, 8 or full page ? burst data transfer in sequential or interleaved order ? burst read with single write ? programmable cas latency: 2, 3 ? 8 column block write and write-per-bit modes ? independent byte operation via dqm 0 ? 3 interface ? auto precharge and auto refresh modes ? 2k refresh cycles/32 ms ? lvttl compatible i/o ? hidden auto precharge for read bursts ordering information type ordering code package description sdr lvttl-version hyb 39s16320tq-6 on request tqfp-100-1 256k 2 32 sgram hyb 39s16320tq-7 on request tqfp-100-1 256k 2 32 sgram hyb 39s16320tq-8 on request tqfp-100-1 256k 2 32 sgram hyb 39s16320tq-10 on request tqfp-100-1 256k 2 32 sgram
hyb 39s16320tq-6/-7/-8 semiconductor group 3 1998-10-01 pin configuration 100 pin tqfp dq28 v ddq dq25 dq24 d15 d12 d13 d14 dq11 v ddq dq9 dqm3 dqm1 mch dq8 n.c. a8 / ap cke dsf clk dq0 dq2 dq1 v dq29 n.c. we cas a9 ras dqm2 dqm0 dq4 dq18 dq23 dq22 dq21 dq20 dq19 dq16 dq7 dq6 dq5 dq3 a2 n.c. a7 a6 a5 a4 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. a3 a1 a0 85 90 95 100 50 40 35 45 1 5 10 15 20 25 30 55 60 65 70 75 80 spp03942 ss ddq v ssq v ddq v dq17 ssq v ddq v dd v ss v ssq v ddq v cs ba v dd ss v ssq v dq10 dd v ss v ddq v ssq v ddq v ssq v dq27 dq26 v ssq dq30 dq31 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. dd v v ssq 20 14 mm 2 0.65 mm pitch (marking side)
hyb 39s16320tq-6/-7/-8 semiconductor group 4 1998-10-01 pin definitions and functions clk clock input dq0 to dq31 datainput/output cke clock enable dqm0 to dqm3 data mask cs chip select v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+ 3.3 v) we write enable v ssq ground for dqs a0 - a9 address inputs nc not connected a8 - ap auto precharge dsf special function enable ba bank select mch must connect high
hyb 39s16320tq-6/-7/-8 semiconductor group 5 1998-10-01 signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sgram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sgram. a0 - a9 input level C during a bank activate command cycle, a0-a9 defines the row address (ra0-ra9) when sampled at the rising clock edge. during a read or write command cycle, a0-a7 defines the column address (ca0-ca7) when sampled at the rising clock edge. in addition to the column address, ca8 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a8 is high, autoprecharge is selected and ba defines the bank to be precharged (low = bank a, high bank b). if a8 is low, autoprecharge is disabled. during a precharge command cycle, a8 is used in conjunction with ba to control which bank(s) to precharge. if a8 is high, both bank a and bank b will be precharged regardless of the state of ba. if a8 is low, then ba is used to define which bank to precharge. ba input level C selects which bank is activated. ba low selects bank a and ba high selects bank b. dq0 - dq31 input output level C data input/output pins operate in the same manner as on conventional drams, with the exception of the block write function. in this case, the dqx pins perform a masking operation.
hyb 39s16320tq-6/-7/-8 semiconductor group 6 1998-10-01 dqm0 - dqm3 input pulse C during read, dqm = 1 turns off the output buffers. during write, dqm = 1 prevents a write to the current memory location. dqm0 corresponds to dq0 - dq7 dqm1 corresponds to dq8 - dq15 dqm2 corresponds to dq16 - dq23 dqm3 corresponds to dq24 - dq31 v dd v ss supply C C power and ground for the input buffers and the core logic. v ddq v ssq supply C C isolated power supply and ground for the output buffers to provide improved noise immunity. dsf input level C dsf is part of the input command to the sgram. if dsf is low, sgram operates in the same way as sdrams. when dsf is high it enables the block write and masked write and special mode register setup cycle. signal pin description (contd) pin type signal polarity function
hyb 39s16320tq-6/-7/-8 semiconductor group 7 1998-10-01 functional block diagrams a0 - a7, ap, ba column addresses address buffer column address counter column a0 - a9, ba row addresses row address buffer counter refresh sense amplifier & i(o) bus column decoder bank 1 1024 x row decoder array memory sense amplifier & i(o) bus column decoder bank 0 1024 x row decoder array memory input buffer output buffer dq0 - dq31 control logic & timing generator dqmx dsf clk cke cs ras cas spb03936 256 x 32 bit 256 x 32 bit we color register mask register
hyb 39s16320tq-6/-7/-8 semiconductor group 8 1998-10-01 functional description general the 16 mbyte sgram is a dual bank 1024 256 32 dram with graphics features of block write and masked write. it consists of two banks. each bank is organized as 1024 rows 256 columns 32 bits. read and write accesses are burst oriented. accesses begin with the registration of an activate command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be accessed. ba selects the bank and address bits a9 - a0 select the row. address bits a7 - a0 registered coincident with the read or write command are used to select the starting column location for the burst access. block writes are not burst oriented and always apply to eight column locations selected by a7 - a3. dqs registered at block write command are used to mask the selected columns. dqs registered coincident with the load special mode register command are used as color data (lc-bit = 1) or persistent mask (lm = 1). if lc and lm are both 1 in the same load special mode register command cycle, the data of the mask and the color register will be unknown. initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees, that the device is preconditioned to each users specific needs. the following sequence is recommended: ? during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. ? the power on voltage must not exceed v dd + 0.3 v on any of the input pins or v dd supplies. ? the clk signal must be started at the same time. ? after power on, an initial pause of 200 m s is required. ? the pause is followed by a precharge of both banks using the precharge command. ? to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. ? once all banks have been precharged, the mode register set command must be issued to initialize the mode register. ? a minimum of eight auto refresh cycles (cbr) are also required. it is also possible to reverse the last two steps of the initialization procedure: first send at least 8 cbr commands, then the lmr command. failure to follow these steps may lead to unpredictable start-up modes.
hyb 39s16320tq-6/-7/-8 semiconductor group 9 1998-10-01 mode register programming the mode register is used to define: a burst length, a burst type, a read latency and an operating mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device looses power. the mode register must be loaded when both banks are idle and the controller must wait the specified time before initiating the subsequent command. violating either of these requirements may result in unknown operation. burst length read and write operations to the sgram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types and a full page burst is available for the sequential type. the full page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. when a read or write command is issued, a block of columns equal to the burst length is selected. the block is defined by address bits a7 - a1 when the burst length is set to 2, by a7-a2 for burst length set to 4 and by a7 - a3 for burst length set to 8. the lower order bit(s) are used to select the starting location within the block. the burst will wrap within the block if a boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved and the type is selected based on the setting of bt bit in the mode register. if bt is set to 0, the burst type is sequential, if bt is 1, the burst type is interleave. read latency the read latency is the delay in clock cycles between the registration of a read command and the availability of the first piece of output data. the latency can be set to 2 or 3 clocks. if a read command is registered at clock edge n and the read latency is 2 clocks, the data will be available by clock edge n + 2. the dqs will start driving already one cycle earlier (n + 1). color register the siemens 16m sgram offers two color registers. if bit m7 is set to 1, two color register mode is specified. operation mode in normal operation, the bits m8 and m9 of mode register (mr) are set 0. the programmed burst length applies to both read and write bursts. when bit m8 is set to 1, burst read and single write mode is selected. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
hyb 39s16320tq-6/-7/-8 semiconductor group 10 1998-10-01 load special mode register (lsmr) the special mode register command is used to load the mask and color registers, which are used in block write and masked write cycles.the data to be written to either the color registers or the mask register is applied to the dqs and the control information is applied to the address inputs. during a lsmr cycle, if the address bit a6 is 1, and all other address inputs are 0, the color register 0 will be loaded with the data on the dqs. if the address bits a6 and a7 are both set equal to 1 and mode register m7 bit was already set to 1, color register 1 will be loaded with the data on the dqs.this color data is used for block write cycles. similarly, when input a5 is 1, and all other address inputs are 0 during a lsmr cycle, the mask register will be loaded with the data on the dqs. never set bit a5 to 1 when a6 and/or a7 are set equal to 1 in the same load special mode register cycle to avoid unknown operation. color registers two color registers (color register 0 and color register 1) are available in the devices. each color register is a 32-bit register which supplies the data during block write cycles. the color register is loaded via a load special mode register command, as shown in the function truth table and will retain data until loaded again with a new data or until power is removed from the sgram. mask register the mask register (or the write-per-bit mask register) is a 32-bit register which acts as a per-bit mask during masked write and masked block write cycles. the mask register is loaded via the load special mode register command and will retain data until loaded again or until power is removed from the sgram.
hyb 39s16320tq-6/-7/-8 semiconductor group 11 1998-10-01 commands the function truth table provides a quick reference of available commands. operation cke n - 1 cke n cs ras cas we dsf dqm ba a8 a0 - a7 device deselect (inhbt) hxhxxxxxxxx no operation (nop) h x l hhhxxxxx load mode register (lmr) hxlllllxx opcode load special mode register (lsmr) hxllllhxx opcode row activate (act) h x l l h h l x ba row addr row active with wpb (actm) hxl l hhhxba row addr read (rd) h x l h l h x x ba l col. read with auto precharge (rda) h x l h l h x x ba h col. write command (wr) hxlhlllxbal col. write command with auto precharge (wra) hxlhlllxbah col. block write (bw) h x l h l l h x ba l col. block write with auto precharge (bwa) h x l h l l h x ba h col. burst terminate (bst) hxl hhl xxxxx precharge single bank (pre) hxllhlxxbalx precharge all banks (preal) hxl l hl xxxhx auto refresh (ref) h h lllh xxxxx self refresh entry (sref (en) hllllh xxxxx self refresh exit (sref (ex) l l h h h l x h x h x h x x x x x x x x x x power down mode entry (pdn-en) h h l l h l x h x h x h x x x x x x x x x x power down mode exit (pdn-ex) l hxxxxxxxxx
hyb 39s16320tq-6/-7/-8 semiconductor group 12 1998-10-01 notes 1. all inputs are latched on the rising edge of the clk. 2. lmr, ref and sref commands should be issued only after both banks are deactivated (preal command). 3. act and actm command should be issued only after the corresponding bank has been deactivated (pre command). 4. wr, wra, rd, rda should be issued after the corresponding bank has been activated (act command). 5. auto precharge command is not valid for full-page burst. 6. bw and bwa commands use mask register data only after actm command. dqm byte masking is active regardless of wpb mask. 7. loading mask register: initiate an lsmr cycle with address pin a5 = 1 to load the mask register with the mask data present on dq pins. except a5, all other address pins must be 0 during lsmr cycle while loading the mask register. 8. loading color register: initiate an lsmr cycle with address pin a6 = 1 to load the color register with the color input data on dq pins. address pin a7 selects color register. except a6 and a7, all other address pins must be 0 during lsmr cycle while loading a color register. if one color register mode is enabled, all address pins, except a6, must be 0 during lsmr cycle. 9. if bw or bwa operation is initiated and 2-color register mode is initialized by the mode register, address a0 selects the desired color register for the operation. if a0 = 0, color register 0 will be used, if a0 = 1, color register 1. 10.any write or block write cycles to the selected bank/row while active will be masked according to the contents of the mask register, in addition to the dqm signals and the column/byte mask information (the later for block writes only). 11.block writes are not burst oriented and always apply to the eight column locations selected by a7 - a3. 12.addressline a9 is always x with the exception of two commands: in lmr and lsmr commands it provides opcode (see description mode and special mode register). in act and actm commands it provides the address bit 9 of the row address.
hyb 39s16320tq-6/-7/-8 semiconductor group 13 1998-10-01 address input for mode set (mode register functions) a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 write mode cas latency bt burst length address bus (ax) mode register (mx) operation mode m8 m9 mode normal 00 multiple burst 0 1 burst type m3 type sequential interleave 0 1 m6 m5 m4 latency cas latency 000 reserved 00 1 reserved 0 1 0 2 0 11 3 1 00 reserved 1 0 1 11 0 reserved 111 address input for mode set (mode register functions) 1 1 1 1 0 0 0 0 m2 1 2 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 m1 0 m0 8 4 length burst length sequential interleave full page 1 2 4 8 spb03935 cr with single write 0 m7 1 color register two color register one color register registers reserved reserved reserved reserved reserved reserved reserved reserved reserved
hyb 39s16320tq-6/-7/-8 semiconductor group 14 1998-10-01 burst length and sequence full page burst full page burst is an extension of the above tables of sequential addressing with the burst length being 256. burst of two starting address (column address a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 burst of four starting address (column address a1 - a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1, 2, 3 0, 1, 2, 3 1 1, 2, 3, 0 1, 0, 3, 2 2 2, 3, 0, 1 2, 3, 0, 1 3 3, 0, 1, 2 3, 2, 1, 0 burst of eight starting address (column address a1 - a0) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 2 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 3 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 4 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 5 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 6 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 7 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
hyb 39s16320tq-6/-7/-8 semiconductor group 15 1998-10-01 special mode register functions note: if only one color register is in use, a7 is dont care. special mode register naming conventions device deselect (inhbt) the device deselect or inhibit function prevents commands from being executed by the sgram, regardless of whether the clk signal is enabled. the device is effectively deactivated (cs is high). no operation (nop) the nop command is used to perform a no operation to an sgram which is selected (cs is low). this prevents unwanted commands being registered during idle or wait states. the execution of the command(s) already in progress will not be affected. load mode register (lmr) the mode register is loaded via address input pins a9 - a0 . the lmr command can only be issued when both banks are idle, and a subsequent executable command can not be issued until 2 clk cycle latency is met. load special mode register (lsmr) lsmr command is used to load either the color register(s) or the mask register at a time. the control information is provided on inputs a9 - a0, while the data for the color or mask register is provided on the dqs. the lsmr command can be issued when both banks are idle, or one or both are active but with no read, write or block write accesses in progress. address bits functions a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 000100000 load mask register 0 001000000 load color register 0 0 011000000 load color register 1 address bit name special name function a5 lm load mask enable a6 lc load color enable a7 scr select color register
hyb 39s16320tq-6/-7/-8 semiconductor group 16 1998-10-01 active (act) the act command is used to open (or activate) a row in a particular bank. the value on ba selects the bank and the address provided on input pins a9 - a0 selects the row. this row remains open for accesses until a precharge command is issued to the bank. a precharge command must be issued before opening a different row in the same bank. active with wpb (actm) actm command is similar to the act command, except that the write-per-bit mask is activated. any write or block write cycles to the selected bank/row while active will be masked according to the contents of the mask register. read (rd) the read command is used to initiate a burst read access from an active row. the value on ba selects the bank and the address provided on inputs a7 - a0 selects the starting column location. the value on a8 determines whether or not auto precharge is used. if a8 is 1, auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. if a particular dqm was registered high, the corresponding dqs appearing 2 clocks later on the output pins will be high-z. write (wr) the write command is used to initiate a burst write access to an active row. the value on ba selects the bank and the address provided on inputs a7 -a0 selects the starting column location. the value on a8 determines whether or not auto precharge is used. if a8 is 1, auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. if a particular dqm is registered high, the corresponding data inputs will be ignored and the write will not be executed to that byte location. block write (bw) the block write command is used to write a single data value to the block of eight consecutive column locations addressed by inputs a7 - a3 . the data is provided by the color register which must be loaded prior to the block write cycle by invoking lsmr cycle. if the two color register option is enabled, the address line a0 is used to select the desired color register. a 0 at a0 selects color register 0, a 1 color register 1. the input data on dqs which is registered coincident with the block write command is used to mask specific column/byte combinations within the block. the dqm signals operate the same way as for write cycles, but are applied to all eight columns in the selected block.
hyb 39s16320tq-6/-7/-8 semiconductor group 17 1998-10-01 precharge (pre) the precharge command is used to deactivate the open row in a particular bank or the open row in both banks. the bank(s) will be available for row access some specified time ( t rp ) after the precharge command is issued. input a8 determines whether one or both banks are to be precharged, input ba selects the bank. if a8 is 1, both banks are to be precharged and ba is don't care. once a bank is precharged (or deactivated), it is in the idle state and must be activated prior to any read, write, or block write commands being issued to that bank. auto precharge (prea) the auto precharge feature allows the user to issue a read, write, or block write command that automatically performs a precharge upon the completion of the block write access or read or write burst, except in the full page burst mode, where it has no effect. the use of this feature eliminates the need to manually issue a precharge command during the functional operation of the sgram. burst terminate (bst) the burst terminate command is used to truncate either fixed-length or full page bursts. auto refresh (ref) auto refresh is used to refresh the various rows in the sgram and is analogous to cas-before- ras (cbr) in drams. this command must be issued each time a refresh is required. the addressing is generated by the internal refresh counter, therefore, the address bits are don't care during a cbr cycle. the sgram requires that 2048 rows to be refreshed every 32 ms ( t ref ). this refresh can be accomplished either by providing an auto refresh command every 15.6 m s or all 2048 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rc ) once every 32 ms. self refresh (sref) the self refresh command can be used to retain data in the sgram, even if the rest of the system is powered down. when in the self refresh mode, the sgram retains data without external clocking. once the sref command is registered, all the inputs to the sgram become don't care with the exception of cke, which must remain low. once sref mode is engaged, the sgram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sgram may remain in self refresh mode for an indefinite period. the procedure for exiting requires a sequence of commands. first, the system clock must be stable prior to cke going high. once cke is high, the sgram must have nop commands issued for t srx , because of the time required for the completion of any bank currently being internally refreshed.
hyb 39s16320tq-6/-7/-8 semiconductor group 18 1998-10-01 detailed description of write commands (wr, masked writes, block write) write command (wr) the following pages illustrate the write operations for various cases. notes 1. input data at dq pins at block write command is registed as a column mask for that block of columns 2. explanation of mnemonics: wr: write command wra: write command with auto precharge bw: block write bwa: block write with auto precharge ba: bank select write bursts are initiated with a write command. the starting column and bank address is provided with the write command, normal or block write is selected, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged automatically at the completion of the burst. during write bursts, the first valid data-in element will be registered coincident with the write command. sub-sequent data elements will be registered on successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional data will be ignored. a full-page burst will continue until terminated (at the end of the page, it will wrap to column 0 and continue). a fixed-length write burst may be followed by, or truncated with a subsequent write burst or block write command (provided that auto precharge was not activated) and a full page write burst can be truncated with a subsequent write burst or block write command. the new write or block write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. to truncate a block write, the t bwc parameter has to be met. a fixed-length write burst may be followed by, or truncated with a subsequent read burst (provided that auto precharge was not activated) and a full-page write burst can be truncated with a subsequent read burst. once the read command is registered, the data inputs will be ignored, and writes will not be executed. summary write commands mnemonic cke cs ras cas we dsf dqm ba a8 address lines wr hlhlll0bal column wra hlhlll0bah column bw h l h l l h 0 ba l column bwa h l h l l h 0 ba h column
hyb 39s16320tq-6/-7/-8 semiconductor group 19 1998-10-01 a fixed-length write burst may be followed by, or truncated with a precharge command to the same bank (provided that auto precharge was not activated) and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles (x = t wr / t ck rounded up to the next whole number) after the clock edge at which the last desired input data element is registered. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last desired data element and ending with the clock edge on which the precharge command is entered. a precharge command issued at the optimum time provides the same operation that would result from the same fixed-length burst with auto precharge. disadvantages of write command with auto precharge 1. back to back read/write bursts can not be initiated. the read/write command with auto precharge will automatically initiate a precharge of the row in the selected bank. most of the applications require subsequent read/write bursts in the same page. 2. the auto precharge command does not allow truncation of fixed-length bursts. it also does not apply to full page bursts. terminating a write burst the fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied one clock edge prior to the burst terminate command will be the last data written. masked writes any write performed to a row that was activated via an active with wpb command is a write-per- bit-mask (wpbm). data is written to the 32 cells at the selected column location subject to the mask stored in the wpb mask register. the data to be written in the dram cell will be according to the following mask: write masking function representation dqm mr dram cell 0 0 mask 1 0 mask 1 1 mask 0 1 write
hyb 39s16320tq-6/-7/-8 semiconductor group 20 1998-10-01 symbolic representation of write masking function if a particular bit in the wpb mask register is a 0, the data appearing on the corresponding dq input will be ignored, and the existing data in the corresponding dram cell will remain unchanged. if a mask data is a 1, the data appearing on the corresponding dq input will be written to the corresponding dram cell. the overall write mask consists of a combination of the dqm inputs, which will mask on a per-byte basis, and the wpb mask register, which masks on a per-bit basis. if a particular dqm signal was registered high, the corresponding byte will be masked. a given bit is written if the corresponding dqm signal registered is 0and the corresponding wpb mask register bit is 1. note that the dqm latency for write is zero. block write (bw) each block write cycle writes a single data value from a color register to the block of eight consecutive column locations addressed by a7 - a3. if single color register mode is enabled, the content of color register 0 is written. if both color registers are enabled, address pin a0 selects the desired color register. address a0 = 0 selects color register 0, address pin a0 = 1 color register 1. the information on the dqs which is registered coincident with the block write command is used to mask specific column/byte combinations within the block. mr & dram cell dq dqm sps03710
hyb 39s16320tq-6/-7/-8 semiconductor group 21 1998-10-01 the table shows the masking of data caused by the registered value on the dq pins, when data is transfered from color register to the 8 succeeding memory locations addressed in the write block command. when a 1 is registered, the color register data will be written to the corresponding dram cells, subject to the dqm and the wpb masking. the overall block write mask consists of a combination of the dqm signals, the wpb mask register and the column/byte mask information. block write timing considerations a block write access requires a time period of t bwc to execute, so in general, the cycle after the block write command should be a nop. however, active or precharge commands to the other bank are allowed. when following a block write with a precharge command to the same bank, t bpl must be met. bit mask mapping of dq bits address within written block byte within data word byte 3 byte 2 byte 1 byte 0 0 dq24 dq16 dq8 dq0 1 dq25 dq17 dq9 dq1 2 dq26 dq18 dq10 dq2 3 dq27 dq19 dq11 dq3 4 dq28 dq20 dq12 dq4 5 dq29 dq21 dq13 dq5 6 dq30 dq22 dq14 dq6 7 dq31 dq23 dq15 dq7
hyb 39s16320tq-6/-7/-8 semiconductor group 22 1998-10-01 block write illustration note: only single color register and byte 0 of color register is used in this example. color register mdq7 = 0 mdq6 = 1 mdq5 = 0 mdq4 = 0 mdq3 = 1 mdq2 = 0 mdq1 = 1 mdq0 = 1 color data i i + 1 i + 2 i + 3 i + 4 i + 5 i + 6 i + 7 column address dq0 = 1 dq1 = 1 dq2 = 1 dq3 = 0 dq4 = 0 dq5 = 1 dq6 = 1 dq7 = 0 column address mask from dq pins mask register mdq7 - mdq0 0 1 0 0 1 0 1 1 write data mask write, keep original data write-per-bit mask data = mask register + dqmi sps03711
hyb 39s16320tq-6/-7/-8 semiconductor group 23 1998-10-01 electrical characteristics absolute maximum ratings operating temperature range .........................................................................................0 to + 70 c storage temperature range..................................................................................... C 55 to + 150 c input/output voltage .......................................................................................... C 0.3 to v dd + 0.3 v power supply voltage v dd / v ddq ............................................................................... C 0.3 to + 4.6 v power dissipation .............................................................................................................. ......... 1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes 1. all voltages are referenced to v ss 2. v ih may overshoot to v dd + 2.0 v for pulse width of < 4 ns with 3.3 v. v il may undershoot to C2.0 v for pulse width < 4 ns with 3.3 v. pulse width measured at 50% points with amplitude measured peak to dc reference. recommended operation and dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v parameter symbol limit values unit notes min. max. input high voltage v ih 2.0 v dd + 0.3 v 1, 2 input low voltage v il C 0.3 0.8 v 1, 2 output high voltage ( i out = C 2.0 ma) v oh 2.4 C v output low voltage ( i out = 2.0 ma) v ol C 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) C 5 5 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C 5 5 m a
hyb 39s16320tq-6/-7/-8 semiconductor group 24 1998-10-01 capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol max. values unit input capacitance (a0 to a9, ba) c i1 4pf input capacitance (ras , cas , we , cs , clk, cke, dqm, dsf) c i2 4pf output capacitance (dq) c io 6pf operating currents t a = 0 to 70 c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter & test condition symb. -6 -7 -8 unit note max. operating current cas latency = 3 cas latency = 2 t rc 3 t rc(min.) , t ck 3 t ck(min.) , i o = 0 ma i cc1 200 180 200 180 180 170 ma 2 precharge standby current in power down mode cke v il(max.) t ck = t ck(min.) cke v il(max.) , t ck = infinite i cc2p i cc2ps 3 2 3 2 3 2 ma 2 precharge standby current in non power down mode cke 3 v ih(min.) t ck 3 t ck(min.) , input changed once in 30 ns cke 3 v ih(min.) , t ck = infinite, no input change i cc2n i cc2ns 60 15 60 15 60 15 ma ma 2 active standby current in power down mode cke v il(max.) , t ck 3 t ck(min.) cke v il(max.) , t ck = infinite i cc3p i cc3ps 3 3 3 3 3 3 ma ma active standby current in non-power down mode cke 3 v ih(min.) , t ck 3 t ck(min.) input changed every 30 ns cke 3 v ih(min.) , t ck = infinite, no input change i cc3n i cc3ns 90 30 90 30 90 25 ma ma burst operating current cas latency = 3 cas latency = 2 burst length = full page t rc = infinite t ck 3 t ck(min.) , i o = 0 ma, 2 banks interleave i cc4 200 200 200 200 190 190 ma ma 2, 3 auto (cbr) refresh current cas latency = 3 cas latency = 2 t rc 3 t rc(min.) i cc5 170 160 170 160 160 160 ma 2 self refresh current cke 0,2 v 2 2 2 ma operating current (block write) t ck 3 t ck(min.) , i o = 0 ma t bwc = t bwc(min.) 200 200 190 ma
hyb 39s16320tq-6/-7/-8 semiconductor group 25 1998-10-01 notes 1. all values are preliminary and subject to future change 2. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 3. these parameters depend on output loading. specified values are obtained with output open.
hyb 39s16320tq-6/-7/-8 semiconductor group 26 1998-10-01 ac characteristics t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symb. limit values unit note -6 -7 -8 min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck3 t ck2 6 8 C C 7 8 C C 8 10 C C ns ns system frequency cas latency = 3 cas latency = 2 C C C C 166 125 C C 143 125 C C 125 100 mhz mhz clock access time (for 30 pf load) cas latency = 3 cas latency = 2 t ac3 t ac2 C C 5.5 5.5 C C 5.5 5.5 C C 6 6 ns ns 2 2 clock high pulse width t ch 2.5C3C3Cns clock low pulse width t cl 2.5C2.5C3Cns cke setup time t cks 2C2C2.5Cns cke hold time t ckh 1C1C1Cns transition time (rise and fall) t t 0.5 10 0.5 10 0.5 10 ns common parameters command setup time t cs 2C2C2.5Cns 3 command hold time t ch 1C1C1Cns address setup time t as 2C2C2.5Cns 3 address hold time t ah 1C1C1Cns active to read or write delay t rcd 18 C 21 C 24 C ns 4 cycle time t rc 66 C 70 C 80 C ns 4 active to precharge command period t ras 48 100k 49 100k 56 100k ns 4 row precharge time t rp 18 C 21 C 24 C ns 4 active bank a to active bank b command period t rrd 12 C 14 C 16 C ns 4 cas to cas delay time (same bank) t ccd 1C1C1Cclk
hyb 39s16320tq-6/-7/-8 semiconductor group 27 1998-10-01 refresh cycle self refresh exit time t srex 2C2C2Cclk 5 total self refresh exit time C 2 clks + t rc C 5 refresh period for non-self refresh t ref C32C32C32ms 6 read cycle data out hold time t oh 2.5C2.5C3Cns data out to low impedance time t lz 0C0C0Cns data out to high impedance time t hz 383838ns 7 write cycle data in setup time t ds 3C2C2.5Cns data in hold time t dh 1C1C1Cns write recovery time t wr 6C7C8Cns block write cycle block write cycle time t bwc 12 C 14 C 16 C ns block write to precharge delay t bwr 12 C 14 C 16 C ns miscellaneous mode register command to command t rsc 2C2C2Cclk ac characteristics (contd) t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symb. limit values unit note -6 -7 -8 min. max. min. max. min. max.
hyb 39s16320tq-6/-7/-8 semiconductor group 28 1998-10-01 notes 1. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. 2. if clock rising time is longer than 1ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 3. if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 4. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: number of clock cycle = specified value of timing period (counted in fractions as a whole number) 5. self refresh exit is a synchronous operation and begins on the second positiv edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 6. any time that the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to wake-up the device. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t 50 pf i/o measurement conditions for t ac and t oh
hyb 39s16320tq-6/-7/-8 semiconductor group 29 1998-10-01 clock frequency and latency parameter symbol speed sort unit -6 -7 -8 clock frequency max. - 166 125 143 125 125 mhz clock cycle time min. t ck 68788ns cas latency min. t aa 32323clk ras to cas delay min. t rcd 33333clk bank active cycle time min. t ras 86767clk bank active cycle time max. t ras 100 100 100 100 100 m s precharge time min. t rp 33333clk bank cycle time min. t rc 11 9 10 9 10 clk last data in to precharge min. t wr 11111clk last data in to active/refresh min. t wr + t rp 44444clk bank to bank delay time min. t rrd 22222clk cas to cas delay time min. t ccd 11111clk write latency fixed t wl 00000clk dqm write mask latency fixed t dqw 00000clk dqm data disable latency fixed t dqz 22222clk clock suspend latency fixed t csl 11111clk block write cycle time fixed t bwc 22222clk
hyb 39s16320tq-6/-7/-8 semiconductor group 30 1998-10-01 package outlines plastic package, p-tqfp-100 thin small outline package, smd (20 14 mm 2 , 0.65 mm lead pitch) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
hyb 39s16320tq-6/-7/-8 semiconductor group 31 1998-10-01 timing diagrams 1 bank activate command cycle 2 burst read operation 3 read interrupted by a read 4 read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 4.4 single bit write cycle 5 burst write operation 5.1 burst write 5.2 load mode register and block write cycle 5.3 read and dqm function 5.4 write and dqm function 6 write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by a read 7 burst write and read with auto precharge 7.1 burst write with auto precharge 7.2 burst read with auto precharge 8 burst termination 8.1 termination of a full page burst read operation 8.2 termination of a full page burst write operation 9 ac parameters 9.1 ac parameters for write timing 9.2 ac parameters for read timing 10 mode register set 11 power on sequence and auto refresh (cbr) 12 clock suspension (using cke) 12.1 clock suspension during burst read cas latency = 2 12.2 clock suspension during burst read cas latency = 3 12.3 clock suspension during burst write cas latency = 2 12.4 clock suspension during burst write cas latency = 3 13 power down mode and clock suspend 14 self refresh (entry and exit)
hyb 39s16320tq-6/-7/-8 semiconductor group 32 1998-10-01 timing diagrams (contd) 15 auto refresh (cbr) 16 random column read (page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17 random column write (page within same bank) 17.1 cas latency = 2 17.2 cas latency = 3 18 random row read (interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19 random row write (interleaving banks) with precharge 19.1 cas latency = 2 19.2 cas latency = 3 20 full page read cycle 20.1 cas latency = 2 20.2 cas latency = 3 21 full page write cycle 21.1 cas latency = 2 21.2 cas latency = 3 22 precharge termination of a burst 22.1 cas latency = 2
hyb 39s16320tq-6/-7/-8 semiconductor group 33 1998-10-01 1. bank activate command cycle rc "h" or "l" t t0 (cas latency = 3) bank b row addr. activate bank b address command clk t nop nop rcd t t1 col. addr. bank b with auto precharge write b t spt03784 bank b row addr. activate bank b row addr. bank a activate bank a t nop rrd t tt
hyb 39s16320tq-6/-7/-8 semiconductor group 34 1998-10-01 2. burst read operation spt03712 clk read a nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop nop dout a3 ck2 latency = 2 t , dq's dout a1 dout a0 dout a2 dout a2 ck3 latency = 3 t , dq's dout a0 dout a1 dout a3 (burst length = 4, cas latency = 2, 3) cas cas
hyb 39s16320tq-6/-7/-8 semiconductor group 35 1998-10-01 3. read interrupted by a read spt03713 clk read a t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout b0 dout b1 dout b2 nop nop nop nop nop nop nop latency = 2 , dq's ck2 t ck3 latency = 3 t , dq's (burst length = 4, cas latency = 2, 3) cas cas read b dout b3 dout b1 dout a0 dout b0 dout b3 dout b2
hyb 39s16320tq-6/-7/-8 semiconductor group 36 1998-10-01 4. read to write interval 4.1. read to write interval commands = 4 + 1 = 5 cycles minimum delay between the read and write dout a0 dq's (burst length = 4, cas latency = 3) dqmx command clk nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before din b0 din b1 spt03787 din b2 dqw nop dqz t nop t t4 t5 write b nop t6 t7 nop t8 "h" or "l" write latency of dqmx
hyb 39s16320tq-6/-7/-8 semiconductor group 37 1998-10-01 4.2. minimum read to write interval the write command must be hi-z before activate cas ck2 latency = 2 t , dq's (burst length = 4, cas latency = 2) clk dqmx command nop t0 t1 bank a nop dqz t t2 t3 din a0 din a1 din a2 spt03413 din a3 1 clk interval read a write a t4 t5 nop nop t6 t7 nop t8 "h" or "l" of dqmx write latency t dqw nop
hyb 39s16320tq-6/-7/-8 semiconductor group 38 1998-10-01 4.3. non-minimum read to write interval cas latency = 3 ck3 cas ck2 latency = 2 t t , dq's , dq's dout a0 (burst length = 4, cas latency = 2, 3) clk dqmx command nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before dout a0 dout a1 din b0 din b0 din b1 din b1 spt03714 din b2 din b2 read a dqz t nop t4 t5 write b nop t6 t7 nop t8 "h" or "l" of dqmx write latency t dqw
hyb 39s16320tq-6/-7/-8 semiconductor group 39 1998-10-01 4.4. single bit write cycle burst write dq's with write per bit enable "h" or "l" bank activate (burst length = 4, cas latency = 2, 3) clk dsf command nop bank activ. t0 t1 nop nop t2 t3 din b0 din b1 din b2 din b3 spt03715 write b nop t4 t5 nop nop t6 t7 nop t8
hyb 39s16320tq-6/-7/-8 semiconductor group 40 1998-10-01 5. burst write operation 5.1. burst write extra data is ignored after termination of a burst. din a3 t4 are registered on the same clock edge. the first data element and the write nop (burst length = 4, cas latency = 2, 3) t0 command dq's clk din a1 t2 nop din a0 write a t1 din a2 nop t3 spt03790 t6 nop nop t5 nop nop t7 nop t8 don't care
hyb 39s16320tq-6/-7/-8 semiconductor group 41 1998-10-01 5.2. load mode register and block write cycle both banks must be idle load mode register burst length set dqx a0 bank activate "h" or "l" (burst length = 8, cas latency = 2, 3) clk command dsf lmr nop rsc t t0 t1 act nop t rcd t2 t3 with color reg. 1 spt03716 with color reg. 0 block write mask column block write mask column nop block write t4 t5 nop bwc t block write t6 t7
hyb 39s16320tq-6/-7/-8 semiconductor group 42 1998-10-01 5.3. read and dqm function dq 7...0 (burst length = 4, cas latency = 2) clk command nop t0 t1 nop nop t2 t3 spt03717 nop t4 t5 nop nop t6 t7 t8 nop read data 0 data 3 data 2 t dqz dqm0 data 1 data 3 data 0 dq 15...8 dqm1 dq 23...16 data 1 data 3 data 2 dqm2 data 1 data 2 data 0 dq 31...24 dqm3
hyb 39s16320tq-6/-7/-8 semiconductor group 43 1998-10-01 5.4. write and dqm function dq 7...0 (burst length = 4, cas latency = 2) clk command nop t0 t1 nop write t2 t3 spt03718 nop t4 t5 nop nop t6 t7 nop data 0 data 3 data 2 dqm0 data 1 data 3 data 0 dq 15...8 dqm1 dq 23...16 data 1 data 3 data 2 dqm2 data 1 data 2 data 0 dq 31...24 dqm3 nop
hyb 39s16320tq-6/-7/-8 semiconductor group 44 1998-10-01 6. write and read interrupt 6.1. write interrupted by a write 6.2. write interrupted by a read spt03791 clk t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop dq's (burst length = 4, cas latency = 2, 3) nop write a din a0 din b0 din b1 din b2 din b3 write b 1 clk interval t5 nop dout b1 dout b0 input data for the write is ignored. , dq's latency = 3 ck3 cas t don't care din a0 don't care (burst length = 4, cas latency = 2, 3) clk , dq's command latency = 2 ck2 cas t nop t0 din a0 write a don't care read b t1 t2 dout b0 nop nop t4 t3 spt03719 appears on the outputs to avoid data contention. dout b2 input data must be removed from the dq's at least one clock cycle before the read data dout b1 dout b3 nop dout b3 nop dout b2 t6 t7 nop t8
hyb 39s16320tq-6/-7/-8 semiconductor group 45 1998-10-01 7. burst write and read with auto precharge 7.1. burst write with auto precharge 7.2. burst read with auto precharge spt03720 clk active nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop latency = 2 dq's latency = 3 dq's (burst length = 2, cas latency = 2, 3) cas cas bank a rp t rp t begin auto precharge bank can be reactivated after write a auto precharge wr t din a1 din a0 wr t din a1 din a0 rp t spt03721 clk with ap nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout a1 dout a2 dout a3 nop nop nop nop nop nop nop latency = 2 , dq's ck2 t dout a3 ck3 latency = 3 t , dq's dout a1 dout a0 dout a2 (burst length = 4, cas latency = 2, 3) cas cas read a rp t rp t bank can be reactivated after begin auto precharge rp t
hyb 39s16320tq-6/-7/-8 semiconductor group 46 1998-10-01 8. burst termination 8.1. termination of a full page burst read operation 8.2. termination of a full page burst write operation spt03722 clk nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout a1 dout a2 dout a3 nop nop burst nop nop nop nop latency = 2 , dq's ck2 t dout a3 ck3 latency = 3 t , dq's dout a1 dout a0 dout a2 (cas latency = 2, 3) cas cas read a the burst ends after a delay equal to the cas latency. terminate input data for the write is masked. t4 latency = 2, 3 dq's nop (cas latency = 2, 3) t0 command cas clk din a1 t2 nop din a0 write a t1 din a2 nop t3 spt03419 t6 burst terminate nop t5 nop nop t7 nop t8 don't care
hyb 39s16320tq-6/-7/-8 semiconductor group 47 1998-10-01 9. ac parameters 9.1. ac parameters for a write timing auto precharge bank b command write with activate write with activate bank a command auto precharge bank a command command bank b addr. a8/ap dqmx dq ba hi-z rcd t ax2 ax1 ax0 ax3 rc t rax rax t as t ah rbx rbx cax activate precharge activate write command command bank a bank a command bank a bank a command spt03723 bx2 bx1 bx0 bx3 ds t t dh ay2 ay1 ay0 ay3 t wr ray ray cbx ray rp t raz raz t8 precharge begin auto bank a clk we cas ras cs cke ck2 t cs t ch cks t ch t t cl t t3 t0 t2 t1 t4 t5 t7 t6 bank b precharge begin auto t ckh t18 burst length = 4, cas latency = 2 t13 t9 t10 t12 t11 t14 t15 t17 t16 t19 t20 t22 t21
hyb 39s16320tq-6/-7/-8 semiconductor group 48 1998-10-01 9.2. ac parameters for a read timing y ac2 hi-z dq activate command bank a read with bank a command auto precharge dqmx addr. a8/ap t rcd t lz t t as rax rax t ah cax rrd t command bank b read with auto precharge activate bank b command ax1 ax0 bx0 activate spt03724 command bank a bx1 t ac2 oh t hz t t ras rc t rbx rbx rbx hz t ray ray t5 t t ba we cas ras t cs cke cks t ch t t cs ch cl ck2 clk t0 t1 t2 t3 t4 precharge bank a begin auto precharge bank b begin auto t ckh burst length = 2, cas latency = 2 t6 t7 t8 t10 t9 t11 t13 t12
hyb 39s16320tq-6/-7/-8 semiconductor group 49 1998-10-01 10. mode register set set command mode register all banks precharge command any command address key t0 t1 t2 t8 rsc t t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03725 t19 t16 t15 t14 t17 t18 cas latency = 2 t20 t21 t22 dsf a0-a7 a8/ap cs we cas ras cke clk
hyb 39s16320tq-6/-7/-8 semiconductor group 50 1998-10-01 11. power on sequence and auto refresh (cbr) inputs must be 200 stable for m s dqmx a8/ap dq addr. ba rp command all banks precharge hi-z ~ ~ t 1st auto refresh command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03726 mode register set command address key 2nd auto refresh command ~ ~ t rc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command any minimum of 8 refresh cycles are required t8 we cas ras cs cke clk required ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t3 is ~ ~ ~ ~ level high t0 t2 t1 t5 t4 t7 t6 t18 2 clock min. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t13 ~ ~ ~ ~ t10 t9 t12 t11 t14 t15 t17 t16 t20 t19 t22 t21
hyb 39s16320tq-6/-7/-8 semiconductor group 51 1998-10-01 12. clock suspension (using cke) 12.1. clock suspension during burst read cas latency = 2 command bank a dqmx addr. dq a8/ap ba read command bank a activate hi-z suspend 1 cycle clock ax0 csl t ax1 cax rax rax spt03727 t suspend 3 cycles suspend 2 cycles clock ax2 csl t clock ax3 hz t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22 csl t
hyb 39s16320tq-6/-7/-8 semiconductor group 52 1998-10-01 12.2. clock suspension during burst read cas latency = 3 csl dqmx addr. dq a8/ap ba bank a activate command hi-z command bank a read ax0 t rax rax cax hz t t suspend 1 cycle clock suspend 2 cycles clock csl ax1 ax2 clock suspend 3 cycles t csl ax3 spt03425 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 53 1998-10-01 12.3. clock suspension during burst write cas latency = 2 bank a dqmx addr. dq a8/ap ba dax0 command write activate command bank a hi-z clock clock 1 cycle suspend suspend 2 cycles dax1 cax rax rax dax3 clock suspend 3 cycles dax2 spt03728 t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 54 1998-10-01 12.4. clock suspension during burst write cas latency = 3 clock suspend 2 cycles bank a dqmx addr. dq a8/ap ba activate command bank a hi-z clock 1 cycle suspend command write dax0 dax1 rax rax cax clock suspend 3 cycles dax2 dax3 spt03427 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 55 1998-10-01 13. power down mode and clock suspend ba clock suspend clock suspend mode entry mode exit addr. dqmx dq a8/ap standby active activate bank a command hi-z read command bank a rax rax cax power down power down mode exit mode entry spt03938 end clock mask clock mask start ax0 ax1 ax2 precharge command bank a ax3 t hz precharge standby any command t7 cas we ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 56 1998-10-01 14. self refresh (entry and exit) ba t self refresh exit command issued addr. dqmx dq a8/ap entry self refresh must be idle all banks hi-z ~ ~ t sb ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03429 exit command begin self refresh srex t rc self refresh command exit any t7 cs cas we ras cke clk ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t ckh t0 t1 t2 ~ ~ ~ ~ t3 t4 ~ ~ ~ ~ t6 t5 t16 cks t t8 t9 t10 t11 t14 t12 t13 t15 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 57 1998-10-01 15. auto refresh (cbr) (minimum interval) addr. dqmx dq a8/ap ba auto refresh command all banks precharge command hi-z t rp t rc spt03729 command command auto refresh command bank a activate rc t rax rax ax2 bank a read ax0 ax1 ax3 cax t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 58 1998-10-01 16. random column read (page within same bank) 16.1. cas latency = 2 ay3 caw addr. ba dq dqmx a8/ap hi-z bank a activate command read command bank a raw raw bank a command aw1 aw0 read bank a command aw2 aw3 cax read ax1 ax0 ay0 precharge command bank a ay1 ay2 cay cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 bank a read command activate command bank a az0 raz raz caz spt03730 az1 burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 59 1998-10-01 16.2. cas latency = 3 ay1 addr. ba dq dqmx a8/ap activate command hi-z bank a raw raw command read command bank a read bank a aw0 aw1 caw cax read bank a command aw3 aw2 ax0 ax1 ay0 cay cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank a ay2 ay3 activate command bank a raz raz spt03432 read bank a command caz burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 60 1998-10-01 17. random column write (page within same bank) 17.1. cas latency = 2 cbx dbx0 bank b command write addr. dqmx dq a8/ap ba command bank b activate bank b command hi-z write dbw2 dbw1 dbw0 dbw3 rbz rbz cbz command bank b activate dby2 write command bank b dby0 dbx1 dby1 precharge command bank b dby3 cby rbz rbz dbz3 write command bank b dbz0 dbz1 dbz2 spt03731 cbz cas ras cke clk we cs t2 ck2 t t0 t1 t3 t4 t5 t6 t15 t7 t8 t9 t10 t13 t12 t11 t14 burst length = 4, cas latency = 2 t19 t17 t16 t18 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 61 1998-10-01 17.2. cas latency = 3 dbw3 addr. dqmx dq a8/ap ba activate bank b command hi-z write bank b command dbw1 dbw0 dbw2 rbz rbz cbz command precharge write write bank b command command bank b dbx1 dbx0 dby0 dby1 bank b dby2 dby3 cbx cby activate command bank b write spt03434 command bank b dbz1 dbz0 rbz rbz cbz cas ras cke clk we cs t2 ck3 t t0 t1 t3 t4 t5 t6 t15 t11 t7 t8 t10 t9 t13 t12 t14 burst length = 4, cas latency = 3 t17 t16 t18 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 62 1998-10-01 18. random row read (interleaving banks) with precharge 18.1. cas latency = 2 ax2 t ba addr. dq dqmx a8/ap bank b activate command hi-z command read bank b rbx rbx rcd t cbx read activate bank a command command bank b command bx2 bx0 ac2 bx1 bank a activate bx3 bx4 rax rax command precharge bank b bx6 bx5 bx7 ax0 ax1 cax rp t rby rby cs we cas ras cke clk t0 high t ck2 t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03732 bank b command ax5 ax3 ax4 read ax6 ax7 cby by1 by0 burst length = 8, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 63 1998-10-01 18.2. cas latency = 3 activate command bank a addr. dqmx dq a8/ap ba read bank b command command bank b activate hi-z bx1 bx0 cbx rbx rcd t rbx t ac3 activate command bank b bx6 bank a command read bx4 bx3 bx2 bx5 bank b precharge command ax0 bx7 ax2 ax1 rax cax rax rp t rby rby precharge bank a command ax7 read bank b command ax5 ax4 ax3 ax6 spt03436 by0 cby t7 we cas ras cs cke clk high ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 8, cas latency = 3 t18 t17 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 64 1998-10-01 19. random row write (interleaving banks) with precharge 19.1. cas latency = 2 dbx4 dax1 ba a8/ap addr. dq dqmx activate command bank a hi-z write command bank a dax0 rax rax rcd t cax command command bank b bank a command dax4 dax2 dax3 bank b activate dax5 dax6 rbx rbx command precharge bank a write dbx0 dax7 dbx1 activate dbx2 dbx3 wr cbx t rp t ray ray clk cke cs ras cas we t0 high ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank a spt03733 command precharge bank b dbx7 dbx5 dbx6 write day0 day1 cay wr t day4 day3 day2 t19 burst length = 8, cas latency = 2 t16 t15 t14 t17 t18 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 65 1998-10-01 19.2. cas latency = 3 dax4 addr. dqmx dq a8/ap ba command bank a bank a activate command hi-z write dax0 dax1 dax3 dax2 rax rcd t rax cax dbx4 dbx0 write command bank b bank b activate command dax6 dax5 dax7 precharge command bank a dbx2 dbx1 dbx3 cbx rbx rbx wr t rp t command bank a activate command bank a write dbx5 dbx6 day0 dbx7 precharge bank b command spt03438 day1 day2 day3 wr ray t cay ray cas ras cke clk we cs t2 high ck3 t t0 t1 t4 t3 t5 t6 t15 t7 t8 t9 t10 t11 t12 t13 t14 burst length = 8, cas latency = 3 t19 t17 t16 t18 t21 t20 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 66 1998-10-01 20. full page read cycle 20.1. cas latency = 2 ba - page address back to zero from the highest order the burst counter wraps during this time interval. addr. dqmx dq a8/ap ~ ~ hi-z command command bank a read bank a activate bank b bank b command command ax activate activate ax +1 ax ~ ~ +2 ax rax rax cax ~ ~ ~ ~ rbx rbx ~ ~ ~ ~ ~ ~ ~ ~ spt03734 bursting beginning with the starting address. burst stop command the burst counter increments and continues terminate when the burst length is satisfied; full page burst operation does not bank b command ax read - 2ax 11 ax + bx bx +1 bx +2 + bx 3 + bx 4 cbx bank b command activate command bank b precharge bx 5 bx+ 6 + rby t rp rby cas ras cke clk cs we ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ high ck2 t t0 t1 t2 ~ ~ ~ ~ t3 t4 ~ ~ ~ ~ t5 t6 t15 t11 t7 t8 t10 t9 t13 t12 t14 burst length = full page, cas latency = 2 t16 t17 t18 t19 t20 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 67 1998-10-01 20.2. cas latency = 3 t14 bx full page burst operation does not terminate when the burst length is satisfied; bursting beginning with the starting address. the burst counter increments and continues ba command bank a a8/ap dqmx dq addr. command activate bank a hi-z read rax rax cax page address back to zero during this time interval. the burst counter wraps from the highest order activate activate bank b bank b command command ax ax 1 + 2 ax + ax ~ ~ ~ ~ - rbx rbx ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ax read bank b command ax 21 - ax 1 + bx bx 1 + cbx t3 clk cke cs ras we cas t0 high ck3 t t1 t2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t4 t5 ~ ~~ ~ ~ ~ t7 t6 t8 ~ ~ t10 t9 t11 t13 t12 spt03440 bank b command activate bank b precharge command burst stop command + +2 bx bx 34 + 5 + bx rby t rp rby t20 burst length = full page, cas latency = 3 t17 t15 t16 t18 t19 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 68 1998-10-01 21. full page write cycle 21.1. cas latency = 2 t14 dbx ~ ~ command activate command activate addr. a8/ap dqmx dq command bank a activate write command bank a hi-z rax rax dax dax 1 + cax page address back to zero the burst counter increments and continues bursting beginning with the starting address. during this time interval. cbx dbx write bank b terminate when the burst length is satisfied; command from the highest order the burst counter wraps bank b bank b 1 dax + dax 2 ~ ~ ~ ~ +3 dax- ~ ~ rbx rbx ~ ~~ ~ ~ ~ dax dax+1 full page burst operation does not data is ignored. dbx dbx +1 + dbx 2 4 3 + dbx+ dbx 5 + t3 clk cke cs cas ras ba we t0 high ck2 t t1 t2 ~ ~~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~ ~ ~ ~ t4 ~ ~ t5 ~ ~ t7 t6 t8 t10 t9 t11 t13 t12 spt03735 precharge command bank b burst stop command command bank b activate +6 rby rby t20 t17 t15 t16 t18 t19 t21 t22 burst length = full page, cas latency = 2
hyb 39s16320tq-6/-7/-8 semiconductor group 69 1998-10-01 21.2. cas latency = 3 t14 full page burst operation does not dbx bursting beginning with the starting address. the burst counter increments and continues terminate when the burst length is satisfied; command bank a a8/ap dq addr. dqmx command activate bank a write hi-z rax rax dax cax from the highest order during this time interval. page address back to zero + the burst counter wraps command bank b activate bank b command activate dax + dax 1 + 2 dax+ rbx rbx dax 3 ~ ~ ~ ~ 1 - ~ ~ dax dax ~ ~ ~ ~ ~ ~ ~ ~ bank b command write ignored. data is dbx dbx 1+ dbx 1 cbx 3 +2 + dbx dbx+ 4 t3 cs we ba cas ras cke clk t0 high ck3 t t1 t2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t4 t5 ~ ~ ~ ~ t7 ~ ~~ ~ t6 t8 t10 t9 t11 t13 t12 spt03442 command bank b activate precharge command bank b command command burst stop burst stop +5 rby rby burst length = full page, cas latency = 3 t20 t17 t15 t16 t18 t19 t21 t22
hyb 39s16320tq-6/-7/-8 semiconductor group 70 1998-10-01 22. precharge termination of a burst 22.1. cas latency = 2 ba rp of a write burst. write data is masked. dqmx a8/ap dq addr. command precharge termination bank a activate command bank a write hi-z dax0 bank a precharge command dax3 dax2 dax1 cax rax rax t of a read burst. spt03736 command bank a activate command bank a activate command bank a read command precharge bank a ay1 ay0 ay2 cay ray ray t rp precharge termination bank a command read caz raz raz t8 cas we ras cs cke clk t3 t high ck2 t0 t2 t1 t5 t4 t6 t7 t18 burst length = 8 or full page, cas latency = 2 t13 t9 t10 t12 t11 t15 t14 t16 t17 t19 t20 t22 t21

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